1. Technology Field
The present invention relates to a data storing method for a rewritable non-volatile memory module and a memory controller and a memory storage device using the same.
2. Description of Related Art
Along with the widespread of digital cameras, cell phones, and MP3 players in recently years, the consumers' demand to storage media has increased drastically. Rewritable non-volatile memory is one of the most adaptable storage media to aforementioned portable electronic devices (for example, notebook computers) due to its many characteristics such as data non-volatility, low power consumption, small volume, non-mechanical structure, and fast access speed. A solid state drive (SSD) is a storage device which uses a flash memory as its storage medium. Thereby, the flash memory industry has become a very important part of the electronic industry in recent years.
NAND flash memories can be categorized into single level cell (SLC) NAND flash memories, multi level cell (MLC) NAND flash memories, and trinary level cell (TLC) NAND flash memories according to the number of bits that would be stored in each memory cell. Each memory cell of a SLC NAND flash memory stores 1-bit data (i.e., “1” and “0”). Each memory cell of a MLC NAND flash memory stores 2-bit data. Each memory cell of a TLC NAND flash memory stores 3-bit data.
In a NAND flash memory, a physical page is composed of several memory cells arranged on the same word line. Since each memory cell of a SLC NAND flash memory stores 1-bit data, in the SLC NAND flash memory, the memory cells arranged on the same word line are corresponding to one physical page.
On the other hand, the floating-gate storage layer of each memory cell in a MLC NAND flash memory can store 2-bit data. Herein each storage state (i.e., “11”, “10”, “01”, and “00”) includes a least significant bit (LSB) and a most significant bit (MSB). For example, in each storage state, the first bit from the left is the LSB, and the second bit from the left is the MSB. Thus, the memory cells arranged on the same word line constitute 2 physical pages. Herein the physical page constituted by the LSBs of the memory cells is referred to as a lower physical page, and the physical page constituted by the MSBs of the memory cells is referred to as an upper physical page. In particular, the write speed of a lower physical page is faster than that of an upper physical page, and when the upper physical page is programmed and an error occurs, data stored in the lower physical page may also be lost.
Similarly, each memory cell in a TLC NAND flash memory can store 3-bit data. Herein each storage state (i.e., “111”, “110”, “101”, “100”, “011”, “010”, “001”, and “000”) includes a LSB (the first bit from the left), a center significant bit (CSB, the second bit from the left), and a MSB (the third bit from the left). Thus, the memory cells arranged on the same word line constitute 3 physical pages. Herein the physical page constituted by the LSBs of the memory cells is referred to as a lower physical page, the physical page constituted by the CSBs of the memory cells is referred to as a middle physical page, and the physical page constituted by the MSBs of the memory cells is referred to as an upper physical page. In particular, when the memory cells arranged on the same word line are programmed, either only the lower physical pages or all the lower physical pages, the middle physical pages, and the upper physical pages are programmed to prevent data loss.
Thereby, how to ensure the accuracy of data stored in a flash memory is one of the major subjects in the industry.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.